1. Field of the Invention
The present invention generally relates to semiconductor devices, device forming substrates, wiring connection testing methods, and manufacturing methods of the semiconductor devices, and more specifically, to a semiconductor device having a wiring connection testing structure formed on a substrate, a device forming substrate, a wiring connection testing method using the wiring connection testing structure, and a manufacturing method of the semiconductor device.
2. Description of the Related Art
Recently, based on improvement in performance of semiconductor devices and the microstructure of the semiconductor devices, it has become necessary to promptly and efficiently detect a defect in a circuit such as bad wiring of the semiconductor device, so that reliability of the semiconductor device can be improved and reduction of manufacturing cost can be realized.
Conventionally, an optical type defect detection device is used as a measure for detecting defects in the circuits of semiconductor devices. However, in this detection device, it is difficult to determine whether the detected defect is an electric defect such as a defect accompanying a short circuit of the wiring. Hence, in this device, it is difficult to detect a defect of a circuit having a high precision.
Because of this, recently, a method for finding a part where the short circuit happens by voltage contrast (hereinafter “VC”) detection has been suggested. The VC detection is for detecting a change of variable density of the wiring by observation using an electron microscope. Such a VC is detected based on the existence of a charge up phenomenon of the wiring.
For example, the following methods are used for detecting the defect part of the wiring by using the above-mentioned VC detection.
FIG. 1 is a first schematic view showing a related art test pattern 1 that is an example of a test pattern for finding a defect part of the wiring by VC detection.
Referring to FIG. 1, in this test pattern 1, a ground wiring pattern 2 is formed on an insulation layer (not shown in FIG. 1) formed on a substrate. Furthermore, a wiring pattern 3 being in an electric floating state against the wiring pattern 2 is provided so as to form a comb teeth-shaped pattern with the wiring pattern 2. That is, the ground wiring pattern and floating wiring pattern which extend in the same direction are reciprocally provided on the insulation layer of the substrate.
For the purpose of detection of the defect part (short circuit part) by using this test pattern, first, an area x1, for example, is observed in a direction crossing the wiring, namely an x1 direction, by using an electron microscope. In this case, a pattern shorting with the wiring pattern 2 has a different image contrast than image contrasts of other wiring patterns among plural wiring patterns 3. While the wiring pattern 3 having no shorted part is in an electric floating state and thereby the charge up phenomenon is generated, the charge up phenomenon is not generated in the wiring pattern 3 shorting with the ground wiring pattern 2, and the difference in surface potential of these wiring patterns 3 is observed as a difference of the variable density in the observation using the electron microscope., namely as a difference of the state of the VC. Because of this, the coordinates in the x1 direction of the shorted part of the wiring pattern 3 can be specified.
Next, an observation of the wiring pattern along the y1 direction perpendicular to the x1 direction is implemented corresponding to the coordinates in the x1 direction, so that the defect part deft of the wiring can be detected. See Japan National Publication of Translated Version of PCT Application No. 2004-501505.
Such a shorted part can be detected by using a test pattern discussed below.
FIG. 2 is a second schematic view showing a related art test pattern 70 that is another example of the test pattern for finding the defect part of the wiring by the VC detection.
Referring to FIG. 2, in this test pattern, a ground wiring pattern 11 is formed on an insulation layer (not shown in FIG. 2) formed on a substrate. Furthermore, a wiring pattern 12 being in an electric floating state against the wiring pattern 11 and including plural cut line segments are provided in the space of in wiring pattern 11. That is, plural cut line segments of the wiring pattern 12 being in an electric floating state are reciprocally provided between neighboring lines of wiring pattern 11.
In a case where the defect part (short circuit part) is detected by using this test pattern, the wiring pattern 12 composed of plural line segments is scanned in the x2 direction in line turn by using the electron microscope so that the wiring pattern where the VC is generated is specified and therefore the shorted part def2 is detected. See Japan Laid-Open Patent Publication No. 2001-305194.
However, in the case of the detection method using the above-mentioned wiring pattern 1, it may be difficult to detect a defect part of a micro-wiring pattern. For example, in the micro-wiring pattern, it is difficult to detect the defect part in the y1 direction in FIG. 1 by using an electron microscope. It may be more difficult to detect a defect part of a more-micro wiring pattern. Furthermore, there is a porous insulation film that is a low dielectric constant insulation film used for preventing an influence of wiring delay. In such a porous insulation film, a shorted part of the wiring may exist in a porous part of the inside of the porous insulation film. It may be difficult to detect such a shorted part formed in the wiring inside of the porous insulation film by observation of the wiring pattern surface.
In addition, in the case of the detection method using the above-mentioned test pattern 70, it is necessary to observe by scanning the cut wiring pattern 12 in the x2 direction, for example. Hence, it may take long time for detection.